The 8Track chip was designed to interface to the LCD scanning hardware inside many higher end system on chip microcontrollers that are used in smartphones, pdas, etc. For instance most of the development work at E Ink uses the PXA255 as a host system. Unfortunately at larger panel sizes this LCD hardware becomes severely taxed and also ends up saturating the host system memory bus. So I thought I would try to build something much lower end, but with some supporting external hardware.

One thing which makes the task of scanning out images for a display update easier is that you always access the frame buffer in a linear way, the same was every time. You don't really need random access to the memory. This gets you thinking about full page burst reads and writes from SDRAM and the like. Originally I was thinking of doing a little CPLD with some counters in it to address fast SRAM, but then I started looking at directly controller mobile SDRAM from a microcontroller. This looked maybe feasible, but then I found a category of products which allows you to use it like synch RAM but you can burst throught the entire memory; you just supply the start address and the clock it up. The only problem is that there is a delay while the chip loads up a new page at the page boundary (typically 256 locations in the sizes I was looking at from Micron).

So now I'm thinking of trying to work out a system with the pixel clock running to the 8Track in 256 word bursts, maybe controlled by some of the timer/counter or PWM stuff inside the LPC chip. The FCLK and LCLK could be software controlled or maybe also run from PWM outputs.

Anyway, here is the block diagram I am shooting for. I'm working on the schematic now in Protel and have the PCB outline nearly finalized.

Block Diagram

The bluetooth module uses a Mitsui transceiver purchased through Sparkfun Electronics with a chip antenna, which I intend on using it in serial port mode.